Semiconductor MOS (metal oxide semiconductor) integrated circuit structures, especially those having a minimum features size of about 2 micron or less (2 micron or less design rules), typically contain two different levels of aluminum metallization. Each such level of metallization includes an array of electrically conducting strips of metal for interconnecting various electronic device elements, such as transistors, integrated in a single crystal silicon semiconductor body. By "different levels" of metallization it is meant that the corresponding metal strips of the "different levels" are located upon different insulating layers which isolate the metallization strips from one another and from the semiconductor body, and hence different levels of metallizations are usually located at differing distances from the underlying semiconductor body. Typically the first level metallization is insulated from the underlying semiconductor body by a field oxide layer located in contact with the silicon body. The metallization strips on different levels, however, ordinarily run at right angles to each other, whereby cross-overs occur at the resulting cross-points or intersections of second level strips with respect to first level strips. It is important that this first and second level metallization be separated by a good insulating layer to prevent spurious electrical connections or "shorts" between first and second level strips, particularly in the neighborhoods of cross-overs.
A typical insulating layer for this purpose is formed by a chemical vapor deposited (CVD) layer of silicon dioxide, deposited after the first level metallization--but before the second level metallization--has been formed. Workers in the art, however, have suspected that undesirable fissures (cracks) are generated through such a silicon dioxide layer, stemming at corner edges of the first level metallization strips. Such cracks give rise to a problem of undesirable short-circuits of second and first level metallizations at cross-overs caused by migration of metal from the second level metallization strips through the cracks down to the first level strips. This problem of short-circuits becomes especially serious in dense arrays (2 micron spacing or less design parameters) of integrated circuit device elements. Since the metal that is sometimes used for the first level metallization, such as aluminum, melts at temperatures below those which would be required to seal the fissures by a high temperature oxide flowing or densification step, such a high temperature step to seal the fissure is not then practical. Moreover, even if the metal is of the kind that does not melt during this high temperature flowing or densification step, undesirable lateral and vertical diffusion of impurities occurs in the silicon body, whereby loss of control over the lateral extents and vertical depths of the corresponding impurity zones will result. Furthermore, when using a phosphorus-rich silicon dioxide ("P-glass") layer as the insulating layer--i.e., a glass layer containing more than about 6 percent phosphorus by weight--flowing or densification of such an insulating layer can result in the formation of shrinkage voids in the phosphorus-rich oxide from the fissures therein, such voids undesirably distorting any apertures that are subsequently formed which touch these voids.
It would therefore be desirable to have a structure which mitigates the problems caused by fissures in the insulating layers.